A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly...

IEEE Journal of Solid-State Circuits 2013 / 03 Vol. 48; Iss. 3

A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design

Danesh, Seyed, Hurwitz, Jed, Findlater, Keith, Renshaw, David, Henderson, Robert
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Volume:
48
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2013.2237672
Date:
March, 2013
File:
PDF, 2.68 MB
english, 2013
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