Low-jitter design method based on n-domain jitter analysis...

Electronics Letters 2009 Vol. 45; Iss. 16

Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

Kishine, K., Inaba, H., Nakamura, Ma., Nakamura, Mi., Ohtomo, Y., Onodera, H.
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Volume:
45
Year:
2009
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el.2009.0717
File:
PDF, 180 KB
english, 2009
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