Design, Modeling, and Hardware Correlation of a...

IEEE Transactions on Advanced Packaging 2004 / 02 Vol. 27; Iss. 1

Design, Modeling, and Hardware Correlation of a 3.2Gb/s/Pair Memory Channel

Beyene, W.T., Yuan, X., Cheng, N., Shi, H.
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Volume:
27
Language:
english
Journal:
IEEE Transactions on Advanced Packaging
DOI:
10.1109/TADVP.2004.825463
Date:
February, 2004
File:
PDF, 1.12 MB
english, 2004
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