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[IEEE 2007 IEEE Workshop on Signal Processing Systems - Shanghai, China (2007.10.17-2007.10.19)] 2007 IEEE Workshop on Signal Processing Systems - Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection
Lin, Su-Hon, Sheu, Ming-Hwa, Wang, Kuang-Hui, Zhu, Jun-Jie, Chen, Si-YingYear:
2007
Language:
english
DOI:
10.1109/SIPS.2007.4387534
File:
PDF, 1.47 MB
english, 2007