Formal Probabilistic Timing Verification in RTL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2013 / 5 Vol. 32; Iss. 5

Formal Probabilistic Timing Verification in RTL

Kumar, Jayanand Asok, Vasudevan, Shobha
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Volume:
32
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/TCAD.2012.2232706
Date:
May, 2013
File:
PDF, 422 KB
english, 2013
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