A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in...

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 2008 / 05 Vol. 55; Iss. 5

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $\mu$m CMOS

Chihun Lee,, Lan-Chou Cho,, Jia-Hao Wu,, Shen-Iuan Liu,
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Volume:
55
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/TCSII.2007.914430
Date:
May, 2008
File:
PDF, 1011 KB
english, 2008
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