Drain current model for a gate all around (GAA) p–n–p–n...

Microelectronics Journal 2013 / 6 Vol. 44; Iss. 6

Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Narang, Rakhi, Saxena, Manoj, Gupta, R.S., Gupta, Mridula
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Volume:
44
Language:
english
Journal:
Microelectronics Journal
DOI:
10.1016/j.mejo.2013.04.002
Date:
June, 2013
File:
PDF, 1.21 MB
english, 2013
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