High-speed architectures for Reed-Solomon decoders

High-speed architectures for Reed-Solomon decoders

Sarwate, D.V., Shanbhag, N.R.
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Volume:
9
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/92.953498
Date:
October, 2001
File:
PDF, 381 KB
english, 2001
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