[IEEE 2012 IEEE CPMT Symposium Japan (Formerly VLSI Packaging Workshop of Japan) - Kyoto, Japan (2012.12.10-2012.12.12)] 2012 2nd IEEE CPMT Symposium Japan - Three-dimensional integration scheme using hybrid wafer bonding and via-last TSV process
Takeda, Kenichi, Aoki, Mayu, Hozawa, Kazuyuki, Furuta, Futoshi, Yanagisawa, Azusa, Kikuchi, Hidekazu, Mitsuhashi, Toshio, Kobayashi, HarufumiYear:
2012
Language:
english
DOI:
10.1109/ICSJ.2012.6523456
File:
PDF, 663 KB
english, 2012