Performance Enhancement in Double-Gated Poly-Si Nanowire...

IEEE Electron Device Letters 2009 / 06 Vol. 30; Iss. 6

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

Horng-Chih Lin,, Wei-Chen Chen,, Chuan-Ding Lin,, Tiao-Yuan Huang,
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Volume:
30
Language:
english
Journal:
IEEE Electron Device Letters
DOI:
10.1109/LED.2009.2018493
Date:
June, 2009
File:
PDF, 489 KB
english, 2009
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