![](/img/cover-not-exists.png)
[IEEE 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Vancouver, BC, Canada (2011.10.3-2011.10.5)] 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems - Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations
Reinsalu, Uljana, Raik, Jaan, Ubar, Raimund, Ellervee, PeeterYear:
2011
Language:
english
DOI:
10.1109/DFT.2011.42
File:
PDF, 334 KB
english, 2011