[IEEE Comput. Soc. Press European Design and Test Conference. ED & TC 97 - Paris, France (17-20 March 1997)] Proceedings European Design and Test Conference. ED & TC 97 - Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks
Benini, L., De Micheli, G., Macii, E., Poncino, M., Scarsi, R.Year:
1997
Language:
english
DOI:
10.1109/EDTC.1997.582409
File:
PDF, 795 KB
english, 1997