![](/img/cover-not-exists.png)
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture
Nonis, Roberto, Grollitsch, Werner, Santa, Thomas, Cherniak, Dmytro, Da Dalt, NicolaVolume:
48
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2013.2272340
Date:
December, 2013
File:
PDF, 2.70 MB
english, 2013