Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
A. Yu. Matrosova, S. A. Ostanin, V. SinghVolume:
74
Language:
english
DOI:
10.1134/S0005117913070084
Date:
July, 2013
File:
PDF, 520 KB
english, 2013