STT-RAM Cache Hierarchy With Multiretention MTJ Designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014 / 6 Vol. 22; Iss. 6

STT-RAM Cache Hierarchy With Multiretention MTJ Designs

Sun, Zhenyu, Bi, Xiuyuan, Li, Hai, Wong, Weng-Fai, Zhu, Xiaochun
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Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2013.2267754
Date:
June, 2014
File:
PDF, 2.88 MB
english, 2014
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