Minimizing accumulative memory load cost on multi-core DSPs...

Journal of Systems Architecture 2013 / 8 Vol. 59; Iss. 7

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory

Hu, Jingtong, He, Yi, Zhuge, Qingfeng, Sha, Edwin H.-M., Xue, Chun Jason, Zhao, Yingchao
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Volume:
59
Language:
english
Journal:
Journal of Systems Architecture
DOI:
10.1016/j.sysarc.2013.05.003
Date:
August, 2013
File:
PDF, 1.03 MB
english, 2013
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