[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Impact of CMOS process scaling and SOI on the soft error rates of logic processes
Hareland, S., Maiz, J., Alavi, M., Mistry, K., Walsta, S., Changhong Dai,Year:
2001
Language:
english
DOI:
10.1109/VLSIT.2001.934953
File:
PDF, 212 KB
english, 2001