[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
Leobandung, E., Nayakama, H., Mocuta, D., Miyamoto, K., Angyal, M., Meer, H.V., McStay, K., Ahsan, I., Allen, S., Azuma, A., Belyansky, M., Bentum, R.-V., Cheng, J., Chidambarrao, D., Dirahoui, B., FuYear:
2005
Language:
english
DOI:
10.1109/.2005.1469238
File:
PDF, 1.45 MB
english, 2005