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[IEEE 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (15-19 Feb. 2004)] 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) - A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process
Lin, J., Haroun, B., Foo, T., Jin-Sheng Wang,, Helmick, B., Randall, S., Mayhugh, T., Barr, C., Kirkpatric, J.Year:
2004
Language:
english
DOI:
10.1109/ISSCC.2004.1332807
File:
PDF, 830 KB
english, 2004