A Discrete-Time Model for the Design of Type-II PLLs With...

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications 2011 / 02 Vol. 58; Iss. 2

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

Wang, Kevin J., Galton, Ian
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Volume:
58
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/TCSI.2010.2072130
Date:
February, 2011
File:
PDF, 889 KB
english, 2011
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