Ultra low energy design exploration of digital decimation...

Microprocessors and Microsystems 2013 / 6 Vol. 37; Iss. 4-5

Ultra low energy design exploration of digital decimation filters in 65nm dual-VT CMOS in the sub-VT domain

Yasser Sherazi, S.M., Rodrigues, Joachim N., Akgun, Omer C., Sjöland, Henrik, Nilsson, Peter
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Volume:
37
Language:
english
Journal:
Microprocessors and Microsystems
DOI:
10.1016/j.micpro.2012.04.002
Date:
June, 2013
File:
PDF, 847 KB
english, 2013
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