[IEEE IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - San Francisco, CA, USA (Dec. 13-15, 2004)] IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

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