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[IEEE 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) - Kgs. Lyngby, Denmark (2012.05.7-2012.05.9)] 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems - Tiempo Asynchronous Circuits System Verilog Modeling Language
Renaudin, Marc, Fonkoua, AlainYear:
2012
Language:
english
DOI:
10.1109/ASYNC.2012.22
File:
PDF, 219 KB
english, 2012