Algorithm, Architecture, and Floating-Point Unit Codesign...

IEEE Transactions on Computers 2014 / 8 Vol. 63; Iss. 8

Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator

Pedram, Ardavan, Gerstlauer, Andreas, Van De Geijn, Robert A.
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Volume:
63
Language:
english
Journal:
IEEE Transactions on Computers
DOI:
10.1109/TC.2014.2315627
Date:
August, 2014
File:
PDF, 2.58 MB
english, 2014
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