Digital-to-Time Synthesizers: Separating Delay Line Error...

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications 2013 / 10 Vol. 60; Iss. 10

Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs

Talwalkar, Sumit A.
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Volume:
60
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/TCSI.2013.2249152
Date:
October, 2013
File:
PDF, 2.29 MB
english, 2013
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