A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation
. Cheng-hsiao Lai, . Ya-chin King, . Shi-yu HuangVolume:
6
Year:
2006
Language:
english
DOI:
10.1109/JSEN.2006.870144
File:
PDF, 620 KB
english, 2006