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A synchronous latency-insensitive RISC for better than worst-case design
Casu, Mario R., Mantovani, PaoloVolume:
48
Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2014.01.003
Date:
January, 2015
File:
PDF, 1.26 MB
english, 2015