Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with...

Solid-State Electronics 2013 / 4 Vol. 82

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

Cheng, C.H., Chou, K.I., Chin, Albert
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Volume:
82
Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2013.02.003
Date:
April, 2013
File:
PDF, 600 KB
english, 2013
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