A low active and leakage power SRAM using a read and write...

A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit

Zhu, Jiafeng, Bai, Na, Wu, Jianhui

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Volume:

Language:

english

Journal:

Microelectronics Journal

DOI:

10.1016/j.mejo.2013.02.009

Date:

April, 2013

File:

PDF, 1.05 MB

english, 2013

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