Implementation of a low power 16-bit radix-4 pipelined SRT...

Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure

Pourashraf, Shirin, Masoud Sayedi, Sayed
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Volume:
44
Language:
english
Journal:
Microelectronics Journal
DOI:
10.1016/j.mejo.2013.08.001
Date:
December, 2013
File:
PDF, 2.56 MB
english, 2013
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