Joint AGC-Equalization Algorithm and VLSI Architecture for...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2007 / 02 Vol. 15; Iss. 2

Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

Lai, Jyh-Ting (Justin), Wu, An-Yeu (Andy), Lee, Chien-Hsiung
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
15
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2007.893593
Date:
February, 2007
File:
PDF, 795 KB
english, 2007
Conversion to is in progress
Conversion to is failed