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Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip
Wang, Chifeng, Bagherzadeh, NaderVolume:
38
Language:
english
Journal:
Microprocessors and Microsystems
DOI:
10.1016/j.micpro.2013.09.006
Date:
June, 2014
File:
PDF, 3.08 MB
english, 2014