Technology mapping for low power in logic synthesis

Technology mapping for low power in logic synthesis

Vivek Tiwari, Pranav Ashar, Sharad Malik
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Volume:
20
Year:
1996
Language:
english
Pages:
26
DOI:
10.1016/0167-9260(96)00002-8
File:
PDF, 1.63 MB
english, 1996
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