Power-gating technique for network-on-chip buffers

Power-gating technique for network-on-chip buffers

Casu, M.R., Zamboni, M., Yadav, M.K.
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Volume:
49
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el.2013.3225
Date:
November, 2013
File:
PDF, 187 KB
english, 2013
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