Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 / 1 Vol. 23; Iss. 1

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Cai, Yici, Deng, Chao, Zhou, Qiang, Yao, Hailong, Niu, Feifei, Sze, Cliff N.
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Volume:
23
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2014.2300174
Date:
January, 2015
File:
PDF, 1.50 MB
english, 2015
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