[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Testing of switch blocks in TSV-reduced Three-Dimensional FPGA
Maebashi, Kouta, Namba, Kazuteru, Kitakami, MasatoYear:
2013
DOI:
10.1109/DFT.2013.6653623
File:
PDF, 190 KB
2013