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[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Volume 3728 || Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation
Paliouras, Vassilis, Vounckx, Johan, Verkest, DiederikVolume:
10.1007/11
Year:
2005
Language:
english
DOI:
10.1007/11556930_34
File:
PDF, 236 KB
english, 2005