![](/img/cover-not-exists.png)
[IEEE 2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010 - Taipei, Taiwan (2010.01.18-2010.01.21)] 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) - Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Xin-Wei Shih,, Chung-Chun Cheng,, Yuan-Kai Ho,, Chang, Yao-WenYear:
2010
Language:
english
DOI:
10.1109/ASPDAC.2010.5419850
File:
PDF, 406 KB
english, 2010