Real-Time Visual Saliency Architecture for FPGA With...

IEEE Transactions on Industrial Informatics 2014 / 8 Vol. 10; Iss. 3

Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation

Barranco, Francisco, Diaz, Javier, Pino, Begona, Ros, Eduardo
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Volume:
10
Language:
english
Journal:
IEEE Transactions on Industrial Informatics
DOI:
10.1109/TII.2014.2319581
Date:
August, 2014
File:
PDF, 1.64 MB
english, 2014
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