Low-Power Leading-Zero Counting and Anticipation Logic for...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2008 / 07 Vol. 16; Iss. 7

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

Dimitrakopoulos, Giorgos, Galanopoulos, Kostas, Mavrokefalidis, Christos, Nikolos, Dimitris
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Volume:
16
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2008.2000458
Date:
July, 2008
File:
PDF, 995 KB
english, 2008
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