Demonstrating HW–SW Transient Error Mitigation...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 / 3 Vol. 23; Iss. 3

Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane

Rodopoulos, Dimitrios, Papanikolaou, Antonis, Catthoor, Francky, Soudris, Dimitrios
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Volume:
23
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2014.2309663
Date:
March, 2015
File:
PDF, 2.68 MB
english, 2015
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