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[Japan Soc. Appl. Phys 1995 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (6-8 June 1995)] 1995 Symposium on VLSI Technology. Digest of Technical Papers - A 6.93-μm/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
Minami, M., Ohki, N., Ishida, H., Yamanaka, T., Ishibashi, K., Shimizu, A., Kure, T., Nishida, T., Nagano, T.Year:
1995
Language:
english
DOI:
10.1109/VLSIT.1995.520836
File:
PDF, 291 KB
english, 1995