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[IEEE 11th IEEE International On-Line Testing Symposium - French Riviera, France (2005.07.8-2005.07.8)] 11th IEEE International On-Line Testing Symposium - Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits
Dhillon, Y.S., Diril, A.U., Chatterjee, A., Metra, C.Year:
2005
Language:
english
DOI:
10.1109/IOLTS.2005.41
File:
PDF, 245 KB
english, 2005