[IEEE 5th IEEE Conference on Nanotechnology, 2005. - Nagoya, Japan (July 11-15, 2005)] 5th IEEE Conference on Nanotechnology, 2005. - Buffer design trade-offs for single electron logic gates
Lageweg, C., Cotofana, S., Vassiliadis, S.Year:
2005
Language:
english
DOI:
10.1109/NANO.2005.1500750
File:
PDF, 250 KB
english, 2005