Design Consideration of Bulk FinFETs Devices With $\hbox{\rm n}^{+}\hbox{/}^{}\hbox{\rm p}^{+}\hbox{/}^{}\hbox{\rm n}^{{+}}$ Gate and $\hbox{\rm p}^{+}\hbox{/}^{}\hbox{\rm n}^{{+}}$ Gate for Sub-50-nm DRAM Cell Transistors

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