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[IEEE 21st International Conference on VLSI Design (VLSID 2008) - Hyderabad, India (2008.01.4-2008.01.8)] 21st International Conference on VLSI Design (VLSID 2008) - A Module Checking Based Converter Synthesis Approach for SoCs

Sinha, Roopak, Roop, Partha S., Basu, Samik
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Year:
2008
Language:
english
DOI:
10.1109/VLSI.2008.109
File:
PDF, 1.43 MB
english, 2008
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