[IEEE 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Austin, TX, USA (2012.10.3-2012.10.5)] 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Low pin count DfT technique for RFID ICs
de Souza Moraes, Marcelo, Herve, Marcos Barcellos, Lubaszewski, Marcelo SoaresYear:
2012
DOI:
10.1109/DFT.2012.6378195
File:
PDF, 1.18 MB
2012