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Gate-Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire GAA MOSFET and Low-Power Strategy in Sub-30-nm-Channel Regime
Y. Omura, S. Nakano, O. HayashiVolume:
10
Year:
2011
Language:
english
DOI:
10.1109/TNANO.2010.2071396
File:
PDF, 1.53 MB
english, 2011