An architecture and an algorithm for fully digital...

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 1995 Vol. 42; Iss. 3

An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs

Soenen, E.G., Geiger, R.L.
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
42
Year:
1995
Language:
english
DOI:
10.1109/82.372864
File:
PDF, 1.08 MB
english, 1995
Conversion to is in progress
Conversion to is failed