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[IEEE 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009) - Xi'an (2009.12.25-2009.12.27)] 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) - Optimization of sub-100nm transistor gate sidewall spacer process for high-performance applications
Chun-Jen Weng,Year:
2009
Language:
english
DOI:
10.1109/edssc.2009.5394193
File:
PDF, 6.22 MB
english, 2009